january 2004 dsc-3101/08 1 ?2004 integrated device technology, inc. features ideal for high-performance processor secondary cache commercial (0c to +70c) and industrial (?40c to +85c) temperature range options fast access times: ? commercial and industrial: 10/12/15/20ns low standby current (maximum): ? 2ma full standby small packages for space-efficient layouts: ? 28-pin 300 mil soj ? 28-pin tsop type i produced with advanced high-performance cmos technology inputs and outputs are lvttl-compatible single 3.3v(0.3v) power supply description the idt71v256sa is a 262,144-bit high-speed static ram organized as 32k x 8. it is fabricated using idt?s high-performance, high-reliability cmos technology. the idt71v256sa has outstanding low power characteristics while at the same time maintaining very high performance. address access times of as fast as 10ns are ideal for 3.3v secondary cache in 3.3v desktop designs. when power management logic puts the idt71v256sa in standby mode, its very low power characteristics contribute to extended battery life. by taking cs high, the sram will automatically go to a low power standby mode and will remain in standby as long as cs remains high. further- more, under full standby mode ( cs at cmos level, f=0), power consump- tion is guaranteed to always be less than 6.6mw and typically will be much smaller. the idt71v256sa is packaged in a 28-pin 300 mil soj and a 28-pin 300 mil tsop type i. functional block diagram a 0 address decoder 262,144 bit memory array i/o control 3101 drw 01 input data circuit we cs v cc gnd a 14 i/o 0 i/o 7 control circuit oe , lower power 3.3v cmos fast sram 256k (32k x 8-bit) idt71v256sa
2 idt71v256sa 3.3v cmos static ram 256k (32k x 8-bit) commercial and i ndustrial temperature ranges recommended operating temperature and supply voltage pin configurations absolute maximum ratings (1) capacitance (t a = +25c, f = 1.0mhz, soj package) truth table (1) dip/soj top view pin descriptions tsop top view 3101 drw 02 5 6 7 8 9 10 11 12 a 12 1 2 3 4 24 23 22 21 20 19 18 17 so28-5 13 14 28 27 26 25 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 v cc we a 8 a 9 a 11 oe a 10 cs i/o 7 16 15 i/o 2 gnd i/o 6 i/o 5 i/o 4 i/o 3 a 14 a 13 , 3101 drw 03 22 23 24 25 26 27 28 1 2 3 4 5 7 6 21 20 19 18 17 16 15 14 13 12 11 10 9 8 a 10 cs i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 gnd i/o 2 i/o 1 i/o 0 a 0 a 1 a 2 so28-8 oe a 11 a 9 a 8 a 13 a 14 a 7 a 6 a 5 a 4 a 3 a 12 we v cc , name description a 0 - a 14 addresses i/o 0 - i/o 7 data input/output cs chip select we write enable oe output enable gnd ground v cc power 3101 tbl 01 note: 1. h = v ih , l = v il , x = don?t care we cs oe i/o function x h x high-z standby (i sb ) xv hc x high-z standby (i sb1 ) h l h high-z output disable hl ld out read llx d in write 3101 tbl 02 notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. input, output, and i/o terminals; 4.6v maximum. symbol rating com'l. unit v cc supply voltage relative to gnd -0.5 to +4.6 v v te rm (2 ) terminal voltage relative to gnd -0.5 to v cc +0.5 v t bias temperature under bias -55 to +125 o c t stg storage temperature -55 to +125 o c p t power dissipation 1.0 w i out dc output current 50 ma 3101 tbl 03 note: 1. this parameter is determined by device characterization, but is not production tested. symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 6 pf c out output capacitance v out = 3dv 7 pf 3101 tbl 04 grade temperature gnd vcc commercial 0 o c to +70 o c0v 3.3v 0.3v industrial -40 o c to +85 o c0v 3.3v 0.3v 3101 tbl 05
6.42 idt71v256sa 3.3v cmos static ram 256k (32k x 8-bit) commercial and i ndustrial temperature ranges 3 recommended dc operating conditions note: 1. v il (min.) = ?2.0v for pulse width less than 5ns, once per cycle. symbol parameter min. typ. max. unit v cc supply voltage 3.0 3.3 3.6 v gnd ground 0 0 0 v v ih input high voltage - inputs 2.0 ____ 5.0 v v ih input high voltage - i/o 2.0 ____ v cc +0.3 v v il input low voltage -0.3 (1 ) ____ 0.8 v 3101 tbl 06 dc electrical characteristics (v cc = 3.3v 0.3v) dc electrical characteristics (1) (v cc = 3.3v 0.3v, v lc = 0.2v, v hc = v cc - 0.2v, commercial and industrial temperture ranges) notes: 1. all values are maximum guaranteed values. 2. f max = 1/t rc , only address inputs cycling at f max ; f = 0 means that no inputs are cycling. symbol parameter 71v256sa10 71v256sa12 71v256sa15 71v256sa20 unit i cc dynamic operating current cs < v il , outputs open, v cc = max., f = f max (2 ) 100 90 85 85 ma i sb standby power supply current (ttl level) cs = v ih , v cc = max., outputs open, f = f max (2 ) 20 20 20 20 ma i sb1 full standby power supply current (cmos level) cs > v hc , v cc = max., outputs open, f = 0 (2 ) , v in < v lc or v in > v hc 2222ma 3101 tbl 0 7 symbol parameter test conditions idt71v256sa unit min. typ. max. |i li | input leakage current v cc = max., v in = gnd to v cc ___ ___ 2a |i lo | output leakage current v cc = max., cs = v ih , v out = gnd to v cc ___ ___ 2a v ol output low voltage i ol = 8ma, v cc = min. ___ ___ 0.4 v v oh output high voltage i oh = -4ma, v cc = min. 2.4 ___ ___ v 3101 tbl 0 8
4 idt71v256sa 3.3v cmos static ram 256k (32k x 8-bit) commercial and i ndustrial temperature ranges ac electrical characteristics (v cc = 3.3v 0.3v, commercial and industrial temperature ranges) figure 1. ac test load figure 2. ac test load (for t clz , t olz , t chz , t ohz , t ow , t whz ) *includes scope and jig capacitances ac test conditions 3101 drw 04 320 ? 30pf* 350 ? data out 3.3v , 3101 drw 05 320 ? 5pf* 350 ? data out 3.3v , input pulse levels input rise/fall times input timing reference levels output reference levels ac test load gnd to 3.0v 3ns 1.5v 1.5v see figures 1 and 2 3101 tbl 09 note: 1. this parameter guaranteed with the ac test load (figure 2) by device characterization, but is not production tested. symbol parameter 71v256sa10 71v256sa12 71v256sa15 71v256sa20 unit min. max. min. max. min. max. min. max. read cycle t rc re ad cycle time 10 ____ 12 ____ 15 ____ 20 ____ ns t aa address access time ____ 10 ____ 12 ____ 15 ____ 20 ns t acs chip select access time ____ 10 ____ 12 ____ 15 ____ 20 ns t cl z (1) chip select to output in low-z 5 ____ 5 ____ 5 ____ 5 ____ ns t chz (1) chip select to output in high-z 080809010ns t oe outp ut enable to output valid ____ 6 ____ 6 ____ 7 ____ 8ns t ol z (1) output e nable to output in low-z 3 ____ 3 ____ 0 ____ 0 ____ ns t ohz (1) output disable to output in high-z 26260708ns t oh output hold from address change 3 ____ 3 ____ 3 ____ 3 ____ ns wri te cycl e t wc write cycle time 10 ____ 12 ____ 15 ____ 20 ____ ns t aw address valid to end-of-write 9 ____ 9 ____ 10 ____ 15 ____ ns t cw chip select to end-of-write 9 ____ 9 ____ 10 ____ 15 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ 0 ____ ns t wp write pulse width 9 ____ 9 ____ 10 ____ 15 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ 0 ____ ns t dw da ta to write time overlap 6 ____ 6 ____ 7 ____ 8 ____ ns t dh data hold from write time 0 ____ 0 ____ 0 ____ 0 ____ ns t ow (1) output active from end-of-write 4 ____ 4 ____ 4 ____ 4 ____ ns t whz (1) write enable to output in high-z 1 8 1 8 1 9 1 10 ns 3101 tbl 10
6.42 idt71v256sa 3.3v cmos static ram 256k (32k x 8-bit) commercial and i ndustrial temperature ranges 5 timing waveform of read cycle no. 1 (1) notes: 1. we is high for read cycle. 2. transition is measured 200mv from steady state. address cs data out oe 3101 drw 06 t rc t aa t oh t acs t clz t chz (2) t oe t olz (2) (2) t ohz (2) data valid , timing waveform of read cycle no. 2 (1,2,4) timing waveform of read cycle no. 3 (1,3,4) notes: 1. we is high for read cycle. 2. device is continuously selected, cs is low. 3. address valid prior to or coincident with cs transition low. 4. oe is low. 5. transition is measured 200mv from steady state. data out cs 3101 drw 08 t acs (5) t clz (5) chz t data valid , address data out 3101 drw 07 t rc t aa t oh t oh data valid previous data valid ,
6 idt71v256sa 3.3v cmos static ram 256k (32k x 8-bit) commercial and i ndustrial temperature ranges timing waveform of write cycle no. 2 ( cs controlled timing) (1,2,3,4) notes: 1. we or cs must be high during all address transitions. 2. a write occurs during the overlap of a low cs and a low we . 3. t wr is measured from the earlier of cs or we going high to the end of the write cycle. 4. if the cs low transition occurs simultaneously with or after the we low transition, the outputs remain in a high-impedance state. 5. if oe is low during a we controlled write cycle, the write pulse width must be the larger of t wp or (t whz + t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during a we controlled write cycle, this requirement does not apply and the write pulse can be as short as the spectified t wp. cs data in address we t wr 3101 drw 10 t aw t dw t wc t cw t dh as t t (5) data valid , notes: 1. a write occurs during the overlap of a low cs and a low we . 2. t wr is measured from the earlier of cs or we going high to the end of the write cycle. 3. during this period, i/o pins are in the output state so that the input signals must not be applied. 4. if the cs low transition occurs simultaneously with or after the we low transition, the outputs remain in a high-impedance state. 5. transition is measured 200mv from steady state. 6. if oe is low during a we controlled write cycle, the write pulse width must be the larger of t wp or (t whz + t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during a we controlled write cycle, this requirement does not apply and the write pulse can be as short as the spectified t wp. timing waveform of write cycle no. 1 ( we controlled timing) (1,2,4,6) cs data in address we data out oe 3101 drw 09 t aw t wr t dw t wc t wp t dh t whz t ow (3) (6) t as (5) (3) t ohz (5) data valid (5) ,
6.42 idt71v256sa 3.3v cmos static ram 256k (32k x 8-bit) commercial and i ndustrial temperature ranges 7 ordering information ? commercial and industrial 300 mil soj (so28-5) tsop type i (so28-8) sa power xx speed x package x process/ temperature range blank i commercial (0c to +70c) industrial (?40c to +85c) y pz idt speed in nanoseconds 3101 drw 11 71v256 device type * available in soj package only. x tape & reel 8 x g restricted hazardous substance device
8 idt71v256sa 3.3v cmos static ram 256k (32k x 8-bit) commercial and i ndustrial temperature ranges corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 sramhelp@idt.com santa clara, ca 95054 fax:408-492-8674 800 544-7726 www.idt.com the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 1/7/00 updated to new format pg. 1, 3, 4, 7 expanded industrial temperature offerings pg. 1, 2, 7 removed 28-pin 300 mil plastic dip package offering pg. 6 removed note no. 1 from write cycle no. 1 diagram; renumbered notes and footnotes pg. 7 revised ordering information pg. 8 added datasheet document history 08/09/00 not recommended for new designs 02/01/01 removed "not recommended for new designs" 06/21/02 pg. 7 added tape and reel option to the ordering information 01/30/04 pg. 7 added "restricted hazardous substance device" to order information.
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